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(R)
L6258
PWM CONTROLLED - HIGH CURRENT DMOS UNIVERSAL MOTOR DRIVER
PRELIMINARY DATA
ABLE TO DRIVE BOTH WINDINGS OF A BIPOLAR STEPPER MOTOR OR TWO DC MOTORS OUTPUT CURRENT UP TO 1.5A EACH WINDING WIDE VOLTAGE RANGE: 12V TO 45V FOUR QUADRANT CURRENT CONTROL, IDEAL FOR MICROSTEPPING AND DC MOTOR CONTROL PRECISION PWM CONTROL NO NEED FOR RECIRCULATION DIODES TTL/CMOS COMPATIBLE INPUTS CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN DESCRIPTION L6258 is a dual full bridge for motor control applications realized in BCD technology, with the capability of driving both windings of a bipolar stepper motor or bidirectionally control two DC motors. L6258 and a few external components form a BLOCK DIAGRAM
RC2 CP VCP1 VCP2 EA_IN2
PowerSO36 ORDERING NUMBER: L6258
complete control and drive circuit. It has high efficiency phase shift chopping that allows a very low current ripple at the lowest current control levels, and makes this device ideal for steppers as well as for DC motors. The power stage is a dual DMOS full bridge capable of sustaining up to 45V, and includes the diodes for current recirculation. The output current capability is 1.5A per winding in continuous mode, with peak start-up current up to 2A. A thermal protection circuitry disables the outputs if the chip temperature exceeds the safe limits.
CC2 EA_OUT2 TRI_0 VS VBOOT
CBOOT
CHARGE PUMP VR + INPUT & SENSE AMP -
+ + -
ERROR AMP TRI_180
C POWER BRIDGE 1
OUT1A
VREF1 I3_1 I2_1 I1_1 I0_1 PH_1 VDD(5V) DAC
C
OUT1B SENSE1B Rs
SENSE1A VR GEN VR (VDD/2) THERMAL PROT. DISABLE VS
VREF1 I3_2 I2_2 I1_2 I0_2 PH_2 TRI_CAP CFREF TRIANGLE GENERATOR TRI_0 TRI_180 DAC VR INPUT & SENSE AMP + -
ERROR AMP
TRI_0
+ +
C POWER BRIDGE 2
OUT2A
TRI_180
-
C
OUT2B SENSE2B Rs
SENSE2A
GND
EA_IN1 RC1
EA_OUT1
D96IN430D
CC1
April 2000
1/18
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6258
ABSOLUTE MAXIMUM RATINGS
Symbol Vs VCC Vref1/Vref2 IO IO Vin Vboot Vboot - Vs Tj Tstg Supply Voltage Logic Supply Voltage Reference Voltage Output Current (peak) Output Current (continuous) Logic Input Voltage Range Bootstrap Supply Maximum Vgate applicable Junction Temperature Storage Temperature Range Parameter Value 50 7 2.5 2 1.5 -0.3 to 7 60 15 150 -55 to 150 Unit V V V A A V V V C C
PIN CONNECTION (Top view)
PWR_GND PH_1 I1_1 I0_1 OUT1A DISABLE TRI_CAP VCC GND VCP1 VCP2 VBOOT VS OUT2A I0_2 I1_2 PH_2 PWR_GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
D96IN432E
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
PWR_GND SENSE1 OUT1B I3_1 I2_1 VS EA_OUT1 EA_IN1 VREF1 SIG_GND VREF2 EA_IN2 EA_OUT2 I2_2 I3_2 OUT2B SENSE2 PWR_GND
2/18
L6258
PIN FUNCTIONS
Pin # 1, 36 2, 17 3 4 5 6 7 8 9 10 11 12 13, 31 14 15 16 18, 19 20, 35 21 22 23 24 25 26, 28 Name PWR_GND PH_1, PH_2 I1_1 I0_1 OUT1A DISABLE TRI_cap VCC (5V) GND VCP1 VCP2 VBOOT VS OUT2A I0_2 I1_2 PWR_GND SENSE2, SENSE1 OUT2B I1_3 I2_2 EA_OUT_2 EA_IN_2 VREF2, VREF1 Description Ground connection (1). They also conduct heat from die to printed circuit copper. These TTL compatible logic inputs set the direction of current flow through the load. A high level causes current to flow from OUTPUT A to OUTPUT B. Logic input of the internal DAC (1). The output voltage of the DAC is a percentage of the Vref voltage applied according to the thruth table of page 7 See pin 3 Bridge output connection (1) Disables the bridges for additional safety during switching. When not connected the bridges are enabled Triangular wave generation circuit capacitor. The value of this capacitor defines the output switching frequency Supply Voltage Input for logic circuitry Power Ground connection of the internal charge pump circuit Charge pump oscillator output Input for external charge pump capacitor Overvoltage input for driving of the upper DMOS Supply voltage input for output stage. They are shorted internally Bridge output connection (2) Logic input of the internal DAC (2). The output voltage of the DAC is a percentage of the VRef voltage applied according to the truth table of page 7 See pin 15 Ground connection. They also conduct heat from die to printed circuit copper Negative input of the transconductance input amplifier (2, 1) Bridge output connection and positive input of the tranconductance (2) See pin 15 See pin 15 Error amplifier output (2) Negative input of error amplifier (2) Reference voltages for the internal DACs, determining the output current value. Output current also depends on the logic inputs of the DAC and on the sensing resistor value Signal ground connection Negative input of error amplifier (1) Error amplifier output (1) See pin 3 See pin 3 Bridge output connection and positive input of the tranconductance (1)
27 29 30 32 33 34
SIG_GND EA_IN_1 EA_OUT_1 I2_1 I3_1 OUT1B
Note: The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1 and 36 are connected together.
3/18
L6258
THERMAL DATA
Symbol Rth j-amb Rth j-case Parameter Thermal Resistance Junction Ambient Thermal Resistance Junction-case (*) Value 20 2.2 Unit C/W C/W
(*) Depending on board and soldering.
ELECTRICAL CHARACTERISTICS (VS = 42V; VCC = 5V; Vboot = 52V; Tj = 25; unless otherwise specified.)
Symbol VS VCC VBOOT VSense VS(off) VSH/VCC14 VCC(off) IS(on) IS(off) ICC (OFF) TSD TSD-H TJ fosc Parameter Test Condition Supply Voltage Logic Supply Voltage Storage Voltage VS = 12 to 45V Max Drop Across Sense Resistor Power on Reset Off Threshold Power on Histeresys Power on Reset Off Threshold VS Quiescent Current Both bridges ON, No Load VS Quiescent Current Both bridges OFF VCC Operative Current DISABLE = LOW Shut Down Temperature Shut Down Hysteresis Thermal Shutdown Triangular Oscillator Frequency (*) CFREF = TBD Min. 12 4.75 VS+6 6 0.3 3.3 4.1 15 7 7 145 25 150 15 Typ. Max. 40 5.25 VS+12 1.25 7.2 Unit V V V V V V V mA mA mA C C C KHz A V
12.5
17.5
TRANSISTORS
IDSS Rds(on) Vf Leakage Current On Resistance Flywheel diode Voltage OFF State ON State If =1.0A 0.6 1 500 0.75 1.4
CONTROL LOGIC
Vin(H) Vin(L) Iin Idis Vref1/ref2 Iref FI = Vref/Vsense VFS Voffset lnput Voltage Input Voltage Input Current (Note 1) Disable Pin Input Current Reference Voltage Vref Terminal Input Current PWM Loop Transfer Ratio DAC Full Scale Precision Current Loop Offset DAC Factor Ratio All Inputs All Inputs 0 < Vin < 5V operating Vref = 1.25 2 0 -150 -10 0 -2 2 Vref = 2.5V I0/I1/I2/I3 = L Vref = 2.5V I0/I1/I2/I3 = H Normalized @ Full scale Value 123 -30 -2 134 +30 +2 mV mV % VCC 0.8 +10 +150 2.5 5 V V A A V A
SENSE AMPLIFIER
Vcm Iinp lnput Common Mode Voltage Range Input Bias -0.7 sense1/sense2 -200 VS+0.7 0 V A dB V/s kHz
ERROR AMPLIFIER
GV SR GBW Open Loop Voltage Gain Output Slew Rate Gain Bandwidth Product Open Loop 70 0.2 400
Note 1: This is true for all the logic inputs except the disable input. (*) Chopping frequency is twice fosc value.
4/18
L6258
FUNCTIONAL DESCRIPTION The circuit is intended to drive both windings of a bipolar stepper motor or two DC motors. The current control is generated through a switch mode regulation. With this system the direction and the amplitude of the load current are depending on the relation of phase and duty cycle between the two outputs of the current control loop. The L6258 power stage is composed by power DMOS in bridge configuration as it is shown in figure 1, where the bridge outputs OUT_A and OUT_B are driven to Vs with an high level at the inputs IN_A and IN_B while are driven to ground with a low level at the same inputs . The zero current condition is obtained by driving the two half bridge using signals IN_A and IN_B with the same phase and 50% of duty cycle. In this case the outputs of the two half bridges are continuously switched between power supply (Vs) and ground, but keeping the differential voltage across the load equal to zero. In figure 1A is shown the timing diagram of the two outputs and the load current for this working condition. Following we consider positive the current flowing into the load with a direction from OUT_A to OUT_B, while we consider negative the current flowing into load with a direction from OUT_B to OUT_A. Now just increasing the duty cycle of the IN_A signal and decreasing the duty cycle of IN_B signal we drive positive current into the load. In this way the two outputs are not in phase, and the current can flow into the load trough the diagonal bridge formed by T1 and T4 when the output OUT_A is driven to Vs and the output OUT_B is driven to ground, while there will be a current recirculation into the higher side of the bridge, through T1 and T2, when both the outputs are at Vs and a current recirculation into the lower side of the bridge, through T3 and T4, when both the outputs are connected to ground. Since the voltage applied to the load for recirculation is low, the resulting current discharge time constant is higher than the current charging time constant during the period in which the current flows into the load through the diagonal bridge formed by T1 and T4. In this way the load current will be positive with an average amplitude depending on the difference in duty cycle of the two driving signals. In figure 1B is shown the timing diagram in the case of positive load current On the contrary, if we want to drive negative current into the load is necessary to decrease the duty cycle of the IN_A signal and increase the duty cycle of the IN_B signal. In this way we obtain a phase shift between the two outputs such to have current flowing into the diagonal bridge formed by T2 and T3 when the output OUT_A is driven to ground and output OUT_B is driven to Vs, while we will have the same current recirculation conditions of the previous case when both the outputs are driven to Vs or to ground. So, in this case the load current will be negative with an average amplitude always depending by the difference in duty cycle of the two driving signals. In figure 1C is shown the timing diagram in the case of negative load current . Figure 2 shows the device block diagram of the complete current control loop. Reference Voltage The voltage applied to VREF pin is the reference for the internal DAC and, together with the sense resistor value, defines the maximum current into the motor winding according to the following relation: 0.5 VREF 1 VREF = IMAX = RS FI RS where Rs = sense resistor value
5/18
L6258
Figure 1. Power Bridge Configuration
VS IN_A T1 OUT_A LOAD T2 OUT_B IN_B
T3
T4
OUTA
OUTB
Fig. 1A
Iload
0
OUTA
OUTB
Fig. 1B
Iload
0
OUTA
OUTB
Fig. 1C 0
Iload
D97IN624
6/18
L6258
Figure 2. Current Control Loop Block Diagram
POWER AMPL. VS
OUTA + VS + OUTB
D97IN625
LOAD RL
Tri_0 INPUT TRANSCONDUCTANCE ERROR AMPL. AMPL. VR VREF I0 I1 I2 I3 PH Gin=1/Ra ib DAC VDAC Rc Cc + ia ic Tri_180 +
LL
RS
VSENSE + Gs=1/Rb SENSE TRANSCONDUCTANCE AMPL.
Input Logic (I0 - I1 - I2 - I3) The current level in the motor winding is selected according to this table:
I3 H H H H H H H H L L L L L L L L I2 H H H H L L L L H H H H L L L L I1 H H L L H H L L H H L L H H L L I0 H L H L H L H L H L H L H L H L Current level % of IMAX No Current 9.5 19.1 28.6 38.1 47.6 55.6 63.5 71.4 77.8 82.5 88.9 92.1 95.2 98.4 100
Phase Input ( PH ) The logic level applied to this input determines the direction of the current flowing in the winding of the motor. High level on the phase input causes the motor current flowing from OUT_A to OUT_B through the load. Triangular Generator This circuit generates the two triangular waves TRI_0 and TRI_180 internally used to generate the duty cycle variation of the signals driving the output stage in bridge configuration. The frequency of the triangular wave defines the switching frequency of the output, and can be adjusted by changing the capacitor connected at TR1_CAP pin : Fref = K
C
where : K = 2 x 10-5
7/18
L6258
Charge Pump Circuit To ensure the correct driving of the high side drivers a voltage higher than Vs is supplied on the Vboot pin. This boostrap voltage is not needed for the low side power DMOS transistors because their sources terminals are grounded. To produce this voltage a charge pump method is used. It is made by using two external capacitors; one connected to the internal oscillator (CP) and the other (Cboot) to storage the overvoltage needed for the driving the gates of the high side DMOS. The value suggested for the capacitors are:
Cboot CP Storage Capacitor Pump Capacitor 100 10 nF nF
Current Control LOOP The current control loop is a transconductance amplifier working in PWM mode. The motor current is a function of the programmed DAC voltage. To keep under control the output current, the curFigure 3. Output comparator waveforms
rent control modulates the duty cycle of the two outputs OUT_A and OUT_B, and a sensing resistor Rs is connected in series with the motor winding in order to produce a voltage feedback compared with the programmed voltage of the DAC . The duty cycle modulation of the two outputs is generated comparing the voltage at the outputs of the error amplifier, with the two triangular wave references . In order to drive the output bridge with the duty cycle modulation explained before, the signals driving each output ( OUTA & OUTB ) are generated by the use of the two comparators having as reference two triangular wave signals Tri_0 and Tri_180 of the same amplitude, the same average value (in our case Vr), but with a 180 of phase shift each other. The two triangular wave references are respectively applied to the inverting input of the first comparator and to the non inverting input of the second comparator . The other two inputs of the comparators are connected together to the error amplifier output voltage resulting by the difference between the programmed DAC. The reset of the comparison between the mentioned signals is shown in fig. 3.
Tri_0 Error Ampl. Output
Tri_180
First Comp. Output
Second Comp. Output
8/18
L6258
In the case of VDAC equal to zero, the transconductance loop is balanced at the value of Vr, so the outputs of the two comparators are signals having the same phase and 50% of duty cycle . As we have already mentioned, in this saturation, the two outputs OUT_A and OUT_B are simultaneously driven from Vs to ground ; and the differential voltage across the load in this case is zero and no current flows in the motor winding. With a positive differential voltage on VDAC (see Fig 2, the transconductance loop will be positively unbalanced respected Vr. In this case being the error amplifier output voltage greater than Vr, the output of the first comparator is a square wave with a duty cycle higher than 50%, while the output of the second comparator is a square wave with a duty cycle lower than 50%. The variation in duty cycle obtained at the outputs of the two comparators is the same, but one is positive and the other is negative with respect to the 50% level. The two driving signals, generated in this case, drive the two outputs in such a way to have switched current flowing from OUT_A through the motor winding to OUT_B. With a negative differential voltage VDAC, the transconductance loop will be negatively unbalanced respected Vr. In this case the output of the first comparator is a square wave with a duty cycle lower than 50%, while the output of the second comparator is a square wave with a duty cycle higher than 50%. The variation in the duty cycle obtained at the outputs of the two comparators is always of the same. The two driving signals, generated in this case, drive the the two outputs in order to have the switched current flowing from OUT_B through the motor winding to OUT_A. Current Control Loop Compensation In order to have a flexible system able to drive motors with different electrical characteristics, the non inverting input and the output of the error amplifier ( EA_OUT ) are available. Connecting at these pins an external RC compensation network it is possible to adjust the gain and the bandwidth of the current control loop. Application data:
VS = 24V LL = 12mH RL = 12 RS = 0.33 RC = to be calculated CC = to be calculated Gs transconductance gain = 1/Rb Gin transconductance gain = 1/Ra Ampl. of the Tria_0_180 ref. = 1.6V (peak to peak) Ra = 40K Rb = 20K Vr = Internal reference equal to VCC/2 (Typ. 2.5V)
these data refer to a typical application, and will be used as an example during the analysis of the stability of the current control loop. The block diagram shows the schematics of the L6258 internal current control loop working in PWM mode; the current into the load is a function of the input control voltage VDAC , and the relation between the two variables is given by the following formula: Iload RS GS = VDAC Gin 1 1 = VDAC Rb Ra VDAC Rb = 0.5 (A) Iload = VDAC Ra RS RS Iload RS is the control voltage defining the load current value is the gain of the input transconGin ductance amplifier ( 1/Ra ) Gs is the gain of the sense transconductance amplifier ( 1/Rb ) Rs is the resistor connected in series to the output to sense the load current In this configuration the input voltage is compared with the feedback voltage coming from the sense resistor, then the difference between this two signals is amplified by the error amplifier in order to have an error signal controlling the duty cycle of the output stage keeping the load current under control. It is clear that to have a good performance of the current control loop, the error amplifier must have an high DC gain and a large bandwidth . Gain and bandwidth must be chosen depending on many parameters of the application, like the characteristics of the load, power supply etc..., and most important is the stability of the system that must always be guaranteed. To have a very flexible system and to have the possibility to adapt the system to any application, the error amplifier must be compensated using an
9/18
where: VDAC
PWM CURRENT CONTROL LOOP Open Loop Transfer Function Analysis Block diagram : refer to Fig. 2.
L6258
RC network connected between the output and the negative input of the same. For the evaluation of the stability of the system, we have to consider the open loop gain of the current control loop:
Aloop = ACerr ACpw ACload ACsense ACpwdB = 20 log 2 VS Vout = Vin Triangular Amplitude 2 24
ACpw|dB = 20 log
1.6
= 29.5dB
where AC... is the gain of the blocks that refers to the error, power and sense amplifier plus the attenuation of the load block. The same formula in dB can be written in this way:
AloopdB = ACerrdB + ACpwdB + ACloaddB + ACsensedB
Moreover, having the two references Tri_0 and Tri_180 a triangular shape it is clear that the transfer function of this block is a linear constant gain without poles and zeros. Load Attenuation The load block is composed by the equivalent circuit of the motor winding (resistance and inductance) plus the sense resistor. We will considered the effect of the Bemf voltage of the motor in the next chapter. The input of this block is the PWM voltage of the power amplifier and as output we have the voltage across the sense resistor produced by the current flowing into the motor winding. The relation between the two variable is : Vsense = Vout RS RL + RS
So now we can start to analyse the dynamic characteristics of each single block, with particular attention to the error amplifier. Power Amplifier The power amplifier is not a linear amplifier, but is a circuit driving in PWM mode the output stage in full bridge configuration. The output duty cycle variation is given by the comparison between the voltage of the error amplifier and two triangular wave references Tri_0 and Tri_180. Because all the current control loop is referred to the Vr reference, the result is that when the output voltage of the error amplifier is equal to the Vr voltage the two output Out_A and Out_B have the same phase and duty cycle at 50%; increasing the output voltage of the error amplifier above the Vr voltage, the duty cycle of the Out_A increases and the duty cycle of the Out_B decreases of the same percentage; on the contrary decreasing the voltage of the error amplifier below the Vr voltage, the duty cycle of the Out_A decreases and the duty cycle of the Out_B increases of the same percentage. The gain of this block is defined by the amplitude of the two triangular wave references; more precisely the gain of the power amplifier block is a reversed proportion of the amplitude of the two references. In fact a variation of the error amplifier output voltage produces a larger variation in duty cycle of the two outputs Out_A and Out_B in case of low amplitude of the two triangular wave references. The duty cycle has the max value of 100% when the input voltage is equal to the amplitude of the two triangular references. The transfer function of this block consist in the relation between the output duty cycle and the amplitude of the triangular references.
Vout = 2 VS (0.5 - DutyCycle) 10/18
so the gain of this block is: ACload = RS Vsense = Vout RL + RS RS
ACloaddB = 20 log
RL + RS
0.33 = -31.4dB 12 + 0.33
ACloaddB = 20 log where: RL =
equivalent resistance of the motor winding RS = sense resistor Because of the inductance of the motor LL, the load has a pole at the frequency : Fpole = 2 1 LL RL + RS
Fpole =
1 = 163Hz 12 10-3 6.28 12 + 0.33
Before analysing the error amplifier block and the sense transconductance block, we have to do this consideration :
L6258
AloopdB = AxdB + BxdB Ax|dB = ACpw|dB + ACload|dB and Bx|dB = ACerr|dB + ACsense|dB this means that Ax|dB is the sum of the power amplifier and load blocks; Ax|dB = (29,5) + (-31.4) = -1.9dB The BODE analysis of the transfer function of Ax is: Bx = - Verr_out Zc =- Vsense Rb
In the case of no external RC network is used to compensate the error amplifier, the typical open loop transfer function of the error plus the sense amplifier is something with a gain around 80dB and a unity gain bandwidth at 400kHz. In this case the situation of the total transfer function Aloop, given by the sum of the AxdB and BxdB is :
The Bode plot of the Ax|dB function shows a DC gain of -1.9dB and a pole at 163Hz. It is clear now that (because of the negative gain of the Ax function), Bx function must have an high DC gain in order to increment the total open loop gain increasing the bandwidth too. Error Amplifier and Sense Amplifier As explained before the gain of these two blocks is : BxdB = ACerrdB + ACsensedB Being the voltage across the sense resistor the input of the Bx block and the error amplifier voltage the output of the same, the voltage gain is given by : ib = Vsense Gs = Vsense Verr_out = -(ic Zc) so because ib = ic we have: Vsense 1 1
The BODE diagram shows together the error amplifier open loop transfer function, the Ax function and the resultant total Aloop given by the following equation : AloopdB = AxdB + BxdB The total Aloop has an high DC gain of 78.1dB with a bandwidth of 15KHz, but the problem in this case is the stability of the system; in fact the total Aloop cross the zero dB axis with a slope of -40dB/decade. Now it is necessary to compensate the error amplifier in order to obtain a total Aloop with an high DC gain and a large bandwidth. Aloop must have enough phase margin to guarantee the stability of the system. A method to reach the stability of the system, using the RC network showed in the block diagram, is to cancel the load pole with the zero given by the compensation of the error amplifier. The transfer function of the Bx block with the compensation on the error amplifier is : Zc =- Bx = - Rb Rc - j 1
Rb
1
2 f Cc Rb
ic = -(Verr_out
Zc
)
In this case the Bx block has a DC gain equal to the open loop and equal to zero at a frequency given by the following formula : Fzero = 1
Rb
= -(Verr_out
1
Zc
)
2 Rc Cc
11/18
L6258
In order to cancel the pole of the load, the zero of the Bx block must be located at the same frequency of 163Hz; so now we have to find a compromise between the resistor and the capacitor of the compensation network. Considering that the resistor value defines the gain of the Bx block at the zero frequency, it is clear that this parameter will influence the total bandwidth of the system because, annulling the load pole with the error amplifier zero, the slope of the total transfer function is -20dB/decade. So the resistor value must be chosen in order to have an error amplifier gain enough to guarantee a desired total bandwidth . In our example we fix at 35dB the gain of the Bx block at zero frequency, so from the formula: Bx_gain@zero freq. = 20 log Rc where: Rb = 20K Rb We can see that the effect of the load pole is cancelled by the zero of the Bx block ; the total Aloop cross a the 0dB axis with a slope of -20dB/decade, having in this way a stable system with an high gain at low frequency and a bandwidth of around 8KHz. To increase the bandwidth of the system, we should increase the gain of the Bx block, keeping the zero in the same position. In this way the result is a shift of the total Aloop transfer function up to a greater value. Effect of the Bemf of the stepper motor on the current control loop stability In order to evaluate what is the effect of the Bemf voltage of the stepper motor we have to look at the load block :
OUT+
Bemf
we have : Rc = 1.1M Therefore we have the zero with a 163Hz the capacitor value :
Cc = 1
R
L
2 Fzero Rc
=
1
6 6.28 163 1.1 10
= 880pF
L
L
Now we have to analyse how the new Aloop transfer function with a compensation network on the error amplifier is. The following bode diagram shows : - the Ax function showing the position of the load pole - the open loop transfer function of the Bx block - the transfer function of the Bx with the RC compensation network on the error amplifier - the total Aloop transfer function that is the sum of the Ax function plus the transfer function of the compensated Bx block.
R
to Sense
S
Amplifier
OUT-
The schematic now shows the equivalent circuit of the stepper motor including a sine wave voltage generator of the Bemf. The Bemf voltage of the motor is not constant, its value changes depending on the speed of the motor. Increasing the motor speed the Bemf voltage increases : Bemf = Kt where: Kt is the motor constant is the motor speed in radiant per second The formula defining the gain of the load considering the Bemf of the stepper motor becomes: (VS - Bemf) VS RS RL + RS
ACload =
Vsense = Vout
ACload =
VS - Bemf
VS
RS RL + RS
12/18
L6258
VS - Bemf RS ACloaddB = 20 log RL + RS VS we can see that the Bemf influences only the gain of the load block and does not introduce any other additional pole or zero, so from the stability point of view the effect of the Bemf of the motor is not critical because the phase margin remains the same. Practically the only effect of the Bemf is to limit the gain of the total Aloop with a consequent variation of the bandwidth of the system. APPLICATION INFORMATION A typical application circuit is shown in Fig.4. Note: For avoid current spikes on falling edge of DISABLE a "DC reaction" would be added to the ERROR Amplifier. (R1-R2 on Fig. 4). Interference Due to the fact that the circuit operates with switch mode current regulation, to reduce the effect of the wiring inductance a good capacitor (100nF) can be placed on the board near the Figure 4: Typical Application Circuit. package, between the power supply line (pin 13,31) and the power ground (pin 1,36,18,19) to absorb the small amount of inductive energy. It should be noted that this capacitor is usually required in addition to an electrolytic capacitor, that has poor performance at the high frequencies, always located near the package, between power supply voltage (pin 13,31) and power ground (pin 1,36,18,19), just to have a current recirculation path during the fast current decay or during the phase change. The range value of this capacitor is between few F and 100F, and it must be chosen depending on application parameters like the motor inductance and load current amplitude. A decoupling capacitor of 100nF is suggested also between the logic supply and ground. A non inductive resistor is the best way to implement the sensing. Whether this is not possible, some metal film resistor of the same value can be paralleled. The two inputs for the sensing of the winding motor current (SENSE_A & SENSE_B) should be connected directly on the sensing resistor Rs terminals, and the path lead between the Rs and the two sensing inputs should be as short as possible.
VCP1 10nF
0.33 10 21 20 OUT2B SENSE2 M 14 9 7 35 34 OUT2A SENSE1 0.33 OUT1B OUT1A VS PWR_GND VS 12mH 10
VCP2 VBOOT
11 12
STEPPER MOTOR
100nF
GND TRI_CAP
1nF PH1 I0_1 I1_1 I2_1 I3_1 PH2 I0_2 I1_2 I2_2 I3_2 DISABLE
L6258
2 4 3 32 33 17 15 16 23 22 6 29 EA_OUT1 1M 30 EA_IN2 25 EA_OUT2 1M
5 13,31 1,36 18,19 8
SOP36 PACKAGE
VDD SIG_GND
VDD(5V)
27
28 26 24
VREF1 VREF2
VREF
EA_IN1
820pF
820pF
D97IN626D
R1 1M
R2 1M
13/18
L6258
Motor Selection Some stepper motor have such high core losses that they are not suitable for switch mode current regulation. Furthermore, some stepper motors are not designed for continuous operating at maximum current. Since the circuit can drive a constant current through the motor, its temperature might exceed, both at low and high speed operation. Unused Inputs Unused inputs should be connected to the proper voltage levels in order to get the highest noise immunity. OPERATION MODE TIME DIAGRAMS Figure 5: Full step operation mode timing diagram (Phase - DAC input and Motor Current)
Position
5V
0 1 2 3 0 1 2 3 0
Notes on PCB Design We recommend to observe the following layout rules to avoid application problems with ground and anomalous recirculation current. The by-pass capacitors for the power and logic supply must be kept as near as possible to the IC. It's important to separate on the PCB board the logic and power grounds and the internal charge pump circuit ground avoiding that ground traces of the logic signals cross the ground traces of the power signals. Because the IC uses the board as a heat sink, the dissipating copper area must be sized in accordance with the required value of Rthj-amb.
FULL Step Vector
Ph1
Phase 1 Phase 2
I0_1
0 5V 0 5V 0 5V 1 0
Ph2
Ph2
I1_1
DAC 1 Inputs
I2_1
0 5V 0 5V 2 3
Ph1
I3_1
0 5V
I0_2
I3
0 5V
I2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
I1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
I0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
DAC 2 Inputs
I1_2
0 5V
I2_2
0
I3_2
0
95.2%
Motor drive Current 1
19.1%
0
95.2%
Motor drive Current 2
19.1%
0
D97IN629A
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Current level % of IMAX 100 98.4 95.2 92.1 88.9 82.5 77.8 71.4 63.5 55.6 47.6 38.1 28.6 19.1 9.5 No Current
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L6258
Figure 6: Half step operation mode timing diagram (Phase - DAC input and Motor Current)
Position
5V
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
Half Step Vector
Ph1
2 3 1
Phase 1
0 5V 0
Phase 5V 2 I0_1
0 5V
Ph2 4
0 Ph2
I1_1
DAC 1 Inputs
I2_1
0 5V 0 5V 5 6 7
Ph1
I3_1
0 5V
I0_2
DAC 2 Inputs
I1_2
0 5V 0 5V
I3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
I2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
I1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
I0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
I2_2
0
I3_2
0
95.2%
Motor drive Current 1
19.1%
0
95.2%
Motor drive Current 2
19.1%
0
Current level % of IMAX 100 98.4 95.2 92.1 88.9 82.5 77.8 71.4 63.5 55.6 47.6 38.1 28.6 19.1 9.5 No Current
D97IN627B
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L6258
Figure 7: 4 bit microstep operation mode timing diagram (Phase - DAC input and Motor Current)
Position
5V
0
4
8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
Micro Step Vector
Ph1
16 24 8
Phase 1
0 5V 0
Phase 5V 2 I0_1
0 5V
Ph2 32
0 Ph2
I1_1
DAC 1 Inputs
I2_1
0 5V 0 5V 40 48 56
Ph1
I3_1
0 5V
I0_2
DAC 2 Inputs
I1_2
0 5V 0 5V
I2_2
0
I3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
I2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
I1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
I0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
I3_2
0
100% 95.2% 82.5% 63.5% 47.6% 38.1% 19.1% 0%
Motor drive Current 1
0
Motor drive 0 Current 2
Current level % of IMAX 100 98.4 95.2 92.1 88.9 82.5 77.8 71.4 63.5 55.6 47.6 38.1 28.6 19.1 9.5 No Current
D97IN628A
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L6258
mm TYP. inch TYP.
DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S
MIN. 0.10 0 0.22 0.23 15.80 9.40 13.90
MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50
MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547
MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570
OUTLINE AND MECHANICAL DATA
0.65 11.05 10.90 5.80 2.90 0 15.50 0.80 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10(max.) 8 (max.)
0.0256 0.435 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G".
N
N a2 A DETAIL A e3 H lead e A a1 E DETAIL A
c DETAIL B
D a3
36 19
slug BOTTOM VIEW E3
B E2 E1 DETAIL B
0.35 Gage Plane
D1
1
1
8
-C-
S h x 45 b
0.12
M
L
SEATING PLANE G C
AB
PSO36MEC
(COPLANARITY)
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L6258
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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